1    /* 
     2     * Copyright (c) 2013, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     * */
    32    /*
    33     *  ======== InterruptDsp.xdc ========
    34     */
    35    
    36    import ti.sdo.utils.MultiProc;
    37     
    38    /*!
    39     *  ======== InterruptDsp ======== 
    40     *  Vayu/DSP interrupt manager
    41     */
    42    
    43    @ModuleStartup
    44    
    45    module InterruptDsp inherits ti.sdo.ipc.notifyDrivers.IInterrupt
    46    {
    47        /*! @_nodoc */
    48        metaonly struct InterruptDataView {
    49            String      remoteProcName;
    50            Bool        registered;
    51            Bool        enabled;
    52            Bool        intPending;
    53            Ptr         payload;
    54        };
    55        
    56        /*! @_nodoc */
    57        @Facet
    58        metaonly config xdc.rov.ViewInfo.Instance rovViewInfo = 
    59            xdc.rov.ViewInfo.create({
    60                viewMap: [
    61                    ['IncomingInterrupts',
    62                        {
    63                            type: xdc.rov.ViewInfo.MODULE_DATA,
    64                            viewInitFxn: 'viewInitInterrupt',
    65                            structName: 'InterruptDataView'
    66                        }
    67                    ],
    68                ]
    69            });
    70    
    71        /* Total number of cores on Vayu SoC */
    72        const UInt8 NUM_CORES = 7;
    73    
    74        /* Number of Cores in EVE Sub-system */
    75        const UInt8 NUM_EVES = 4;
    76    
    77        /* Number of Cores in DSP Sub-system */
    78        const UInt8 NUM_DSP_CORES = 2;
    79    
    80        /* Number of Internal EVE mailboxes */
    81        const UInt8 NUM_EVE_MBX = 12;
    82    
    83        /* Number of System Mailboxes */
    84        const UInt8 NUM_SYS_MBX = 1;
    85    
    86        /* Base address for the Mailbox subsystem */
    87        config UInt32 mailboxBaseAddr[NUM_EVE_MBX + NUM_SYS_MBX];
    88    
    89        /* 
    90         * Mailbox table for storing encoded Base Address, mailbox user Id,
    91         * and sub-mailbox index.
    92         */
    93        config UInt32 mailboxTable[NUM_CORES * NUM_CORES];
    94    
    95        config UInt32 dspInterruptTable[NUM_CORES];
    96    
    97        config UInt32 procIdTable[NUM_CORES];
    98    
    99    internal:
   100    
   101        config UInt eve0ProcId     = MultiProc.INVALIDID;
   102        config UInt eve1ProcId     = MultiProc.INVALIDID;
   103        config UInt eve2ProcId     = MultiProc.INVALIDID;
   104        config UInt eve3ProcId     = MultiProc.INVALIDID;
   105        config UInt dsp0ProcId     = MultiProc.INVALIDID;
   106        config UInt dsp1ProcId     = MultiProc.INVALIDID;
   107        config UInt benelliProcId  = MultiProc.INVALIDID;
   108    
   109        /*! Function table */
   110        struct FxnTable {
   111            Fxn    func;
   112            UArg   arg;
   113        }
   114    
   115        /*!
   116         *  ======== intShmStub ========
   117         *  Stub to be plugged
   118         */
   119        Void intShmStub(UArg arg);
   120        
   121        struct Module_State {        
   122            /* 
   123             * Create a function table of length 8 (Total number of cores in the
   124             * System) for each DSP core.
   125             */
   126            FxnTable   fxnTable[NUM_CORES];
   127            /*
   128             * Number of numPlugged counters is equal to the number of combined
   129             * events used by the mailbox interrupts.
   130             */
   131            UInt       numPlugged;  /* # of times the interrupt was registered */
   132        };
   133    } 
   134    /*
   135     *  @(#) ti.sdo.ipc.family.vayu; 1, 0, 0, 0,; 1-23-2013 13:25:35; /db/vtree/library/trees/ipc/ipc-i12/src/ xlibrary
   136    
   137     */
   138