1    /* 
     2     * Copyright (c) 2013, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     * */
    32    /*
    33     *  ======== InterruptBenelli.xdc ========
    34     *
    35     */
    36     
    37    import ti.sdo.utils.MultiProc;
    38    
    39    /*!
    40     *  ======== InterruptBenelli ======== 
    41     *  TI81xx/Ducati based interrupt manager
    42     */
    43    
    44    @ModuleStartup
    45    
    46    module InterruptBenelli inherits ti.sdo.ipc.notifyDrivers.IInterrupt
    47    {
    48        /* Total number of cores on Vayu SoC */
    49        const UInt8 NUM_CORES = 7;
    50    
    51        /* Number of Cores in EVE Sub-system */
    52        const UInt8 NUM_EVES = 4;
    53    
    54        /* Number of Cores in Benelli Sub-system */
    55        const UInt8 NUM_BENELLI_CORES = 1;
    56    
    57        /* Number of Internal EVE mailboxes */
    58        const UInt8 NUM_EVE_MBX = 12;
    59    
    60        /* Number of System Mailboxes */
    61        const UInt8 NUM_SYS_MBX = 1;
    62    
    63        /* Base address for the Mailbox subsystem */
    64        config UInt32 mailboxBaseAddr[NUM_EVE_MBX + NUM_SYS_MBX];
    65    
    66        /*
    67         * Mailbox table for storing encoded Base Address, mailbox user Id,
    68         * and sub-mailbox index.
    69         */
    70        config UInt32 mailboxTable[NUM_CORES * NUM_CORES];
    71    
    72        /* Base address for the Ducati CTRL register */
    73        config UInt32 ducatiCtrlBaseAddr = 0x40001000;
    74    
    75        config UInt32 benelliInterruptTable[NUM_CORES];
    76    
    77        config UInt32 procIdTable[NUM_CORES]; 
    78    internal:
    79    
    80        /*! Statically retrieve procIds to avoid doing this at runtime */    
    81        config UInt eve0ProcId     = MultiProc.INVALIDID;
    82        config UInt eve1ProcId     = MultiProc.INVALIDID;
    83        config UInt eve2ProcId     = MultiProc.INVALIDID;
    84        config UInt eve3ProcId     = MultiProc.INVALIDID;
    85        config UInt dsp0ProcId     = MultiProc.INVALIDID;
    86        config UInt dsp1ProcId     = MultiProc.INVALIDID;
    87        config UInt benelliProcId  = MultiProc.INVALIDID;
    88    
    89        /*! Function table */
    90        struct FxnTable {
    91            Fxn    func;
    92            UArg   arg;
    93        }
    94    
    95        /*! Stub to be plugged for intra-ducati interrupts */
    96        Void intShmMbxStub(UArg arg);
    97        
    98        struct Module_State {        
    99            /* 
   100             * Create a function table of length 8 (Total number of cores in the
   101             * System) for each M4 core.
   102             */
   103            FxnTable   fxnTable[NUM_CORES];
   104            UInt       numPlugged[NUM_EVE_MBX + NUM_SYS_MBX]; /* # of times interrupt registered */
   105        };
   106    } 
   107    /*
   108     *  @(#) ti.sdo.ipc.family.vayu; 1, 0, 0, 0,; 1-23-2013 13:25:34; /db/vtree/library/trees/ipc/ipc-i12/src/ xlibrary
   109    
   110     */
   111